The present invention relates to a semiconductor memory device and a manufacturing method therefor, and more particularly to a large-scale-integrated semiconductor memory device having a capacitor and the manufacturing method therefor.
Recently, as semiconductor manufacturing technology has progressed and the field of application of memory elements has expanded, high storage capacity integrated memory devices have been developed. More particularly, memory cells for dynamic random access memories (DRAMs) consisting of only a capacitor and transistor has promoted large-scale integration of memories.
The density of each new generation of DRAMs has increased by a factor of four with a new generation being developed every three years. Thus, the 4 MB DRAM chip is now in mass-production, the 16 MB DRAM has been designed and is quickly being developed for mass production, and both the 64 MB and 256 MB DRAMs are being researched and developed.
Although the memory cells of such semiconductor memory devices should have sufficiently large capacitances to permit storage, reading and writing of information, the tour-fold increase of density or memory capacity has in practice resulted in only a 40% increase in the effective chip area. Thus the stage of the next generation memory cell is reduced to about one-third the size of the previous generation. Therefore, conventional capacitor designs are proving insufficient to provide adequate cell capacitance because of the smaller areas allotted for the capacitors in succeeding generations of DRAMs. Accordingly, methods have been sought to achieve larger capacitances within a given cell area.
To realize memory devices with integration densities beyond that of 64 MB DRAMs, a novel structure is required to guarantee enough capacitance in an area of 1.5 .mu.m.sup.2 or less. To achieve such a structure, attempts are being made to manufacture a more minute memory cell using the conventional trench capacitor used in 4 MB and 16 MB DRAMs. The biggest problem confronting these attempts is related to the leakage current between the memory cells caused by miniaturization of the memory cell. This leakage current has, for the most part, two paths; one between neighboring trenches, and the other between a storage electrode and its neighboring active region.
Of these two, the leakage current between neighboring trenches can be prevented by the buried-stacked capacitor cell (BSCC) structure, wherein a leakage-current-preventing oxide film is formed before forming the storage electrode inside the trench. However, the problem of leakage current through the contact portion between the storage electrode and its neighboring active region, caused by the impurity diffusion from the contact portion, is not yet solved. This hinders the miniaturization of the memory cell.
A new memory cell which can prevent the above leakage current and which is applicable to 64 MB or higher DRAMs has been suggested by Toshiba Co., Ltd. (see "Process Integration for 64 M DRAM using an Asymmetrical Stacked Trench Capacitor (AST) Cell" by K. Sunouchi et al. IEDM 90, pp. 647-650).
PIG. 1 is a schematic layout for a conventional trench cell, and FIG. 2 is a schematic layout for the aforementioned Toshiba AST cell.
Comparing FIG. 1 with FIG. 2, in the trench cell shown in FIG. 1, trench capacitor T1 is symmetrically arranged with respect to active region D1, while in the AST cell shown in FIG. 2, trench capacitor T1 is asymmetrically arranged with respect to active region D1. Additionally, in the AST cell, the contact portion C1 of a storage electrode used as the capacitor's first electrode is disposed completely within active region D1 and oxide film OX1 is formed on the inner wall of trench capacitor T1, for insulating the trench capacitor from the semiconductor substrate. In FIGS. 1 and 2, reference symbol A denotes the distance between neighboring active regions, B denotes the distance between neighboring trench capacitors, and C denotes the distance between the active region and the trench capacitor. It can be seen that the distance A is the same in FIGS. 1 and 2, while the distances B and C of FIG. 2 are smaller than those of FIG. 1. Since the trench capacitor of an AST cell is asymmetrically arranged, the AST cell has enough distance between the storage electrode's contact portion and its neighboring active region so that leakage current between these two areas can be effectively suppressed. Moreover, the leakage current between neighboring trenches can be prevented by the oxide film OX1 formed on the inner wall of the trench capacitor, thereby realizing memory cell miniaturization.
Therefore, the AST cell can have a larger trench capacitor diameter and hence larger effective surface area regardless of the isolation characteristic of the trench capacitors around it, thereby providing a relatively large storage capacity in a small area.
FIG. 3 is a schematic layout showing a method of manufacturing a conventional semiconductor memory device having a trench cell. The portion defined by the solid line is a mask pattern M1 for forming an active region, the portion defined by the dashed line is a mask pattern P1 for forming a trench capacitor and the portion defined by the dash-dot line is a mask pattern P2 for forming the contact portion. The contact portion connects the transistor's source region with the storage electrode as a first electrode of the trench capacitor. A photoresist pattern is formed on the area except for the portion of the mask pattern P2 for forming the contact portion. Hence, in the subsequent etching step, only the area N is etched to thereby form the contact portion in accordance with pattern P2.
FIGS. 4 to 8 are sectional views of a semiconductor memory device comprising the conventional trench capacitor cell, cut along line a--a' of FIG. 3, and help to explain the method of manufacturing this prior art trench capacitor.
FIG. 4 illustrates a step for forming a trench 10 in the semiconductor substrate 100. First insulating layer 1 and second insulating layer 2 are formed on semiconductor substrate 100 on which field oxide layer 101 has been formed. The first and second insulating layers are formed by sequentially depositing, for example, oxide and nitride layers respectively. Thereafter, second insulating layer 2 is patterned, and then a high temperature oxide (HTO) is deposited over the entire surface area to form third insulating layer 3. Then, a photoresist 4 is coated on third insulating layer 3. Mask pattern P1 for forming the trench capacitor shown in FIG. 3 is applied to form the first photoresist pattern 4 by a conventional exposing and developing process. Then, in sequence the third, second and first insulating layers 3, 2 and 1 and the semiconductor substrate 100 are etched using the first photoresist pattern 4 as an etching mask, to thereby form a trench 10 having a predetermined depth.
FIG. 5 illustrates a step for forming a leakage current preventing layer 11. After removing the first photoresist pattern 4, leakage current preventing layer 11 for preventing leakage current between neighboring trenches is formed on the inner surface of trench 10 by thermally oxidizing the surface portion of semiconductor substrate 100 in trench 10.
FIG. 6 illustrates a step for forming contact portion CA. In order to form contact portion CA for connecting a storage electrode to be formed in the trench 10 with the transistor's source region, a photoresist 5 is coated over the entire surface area after the layer 11 is formed. Then, second photoresist pattern 5 as shown in FIG. 6 is formed by a conventional exposing and developing process, using the mask pattern P2 shown in FIG. 3. Thereafter, a portion of leakage current preventing layer 11 is removed using the second photoresist pattern 5 as a mask, to thereby provide contact portion CA for the storage electrode as a first electrode of the capacitor. According to the above method for forming the contact portion, the contact portion of the storage electrode can be entirely included in the active region. Thus, sufficient distance from the neighboring active region can be secured.
FIG. 7 illustrates the step of forming a storage electrode 13 as a first electrode of the capacitor and of forming a dielectric film 15. After removing second photoresist pattern 5, polycrystalline silicon doped with an impurity is deposited on the entire surface area to form a first conductive layer. This is patterned to provide a storage electrode 13 as the first electrode of the capacitor. Thereafter, dielectric material is coated on the storage electrode 13 to form dielectric film 15 of the capacitor.
FIG. 8 illustrates the step for forming a plate electrode 17 as the second electrode of a capacitor and transistor. A polycrystalline silicon doped with an impurity is deposited on the entire surface area on which dielectric film 15 has been formed, to thereby provide a second conductive layer. This layer is patterned to provide a plate electrode 17 as a second electrode of the capacitor. This completes the capacitor comprised of storage electrode 13, dielectric film 15 and plate electrode 17. Here, reference symbols S1 and S2 represent plate electrode profiles on the active region. This profile is formed by etching the second conductive layer. After completing the capacitor, the gate electrode G, source region 20 and drain region (not shown) are formed by a conventional process to complete the transistor.
In this manufacturing method, patterning the second conductive layer 17 may lead to the profiles S1 or S2 as shown in FIG. 8. If plate electrode 17 has the profile S1, space D occupied by plate electrode 17 will lead to a lack of process margin in manufacturing a highly integrated semiconductor device.
Additionally, if the second conducting layer 17 is excessively etched to form plate electrode 17 having a profile S2, there is a high probability that dielectric film 15 will be exposed to an etchant in the etching step, such that the film may be damaged, which deteriorates the reliability of the memory cell. The same problem will occur in the above AST cell. In a conventional AST cell, such problems are serious since the inter-cell distances are smaller than those of a conventional trench cell.